R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 349

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 312 of 802
Figure 20.4
Perform the following in timer mode (input capture and output compare functions).
To use the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register:
• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register.
To use the TRDGRDi register as the buffer register of the TRDGRBi register:
• Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
For the input capture function, bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the
TRDIOCi pin when registers TRDGRCi and TRDGRDi are also used as buffer registers.
For the output compare function, in reset synchronous PWM mode, complementary PWM mode, and PWM3
mode, bits IMFC and IMFD in the TRDSRi register are set to 1 by a compare match with the TRDi register
when registers TRDGRCi and TRDGRDi are also as buffer registers.
i = 0 or 1
The above applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (low-level output at compare match).
the TRDGRAi register).
Buffer Operation of Output Compare Function
TRDGRCi register
TRDGRAi register
TRDIOAi output
TRDGRCi register
TRDi register
(buffer)
(buffer)
Oct 30, 2009
m-1
Compare match signal
m
TRDGRAi
register
m
n
Comparator
Transfer
n
m+1
TRDi
20. Timer RD