R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 456

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 419 of 802
20.9
Figure 20.24
Table 20.17
Timer RD0
Timer RD1
Timer RD generates the timer RDi (i = 0 or 1) interrupt request based on six sources for each timer RD0 and
timer RD1. The timer RD interrupt uses the single TRDiIC register (bits IR, and ILVL0 to ILVL2), and a single
vector for each timer RD0 and timer RD1. Table 20.17 lists the Registers Associated with Timer RD Interrupt,
and Figure 20.24 shows a Block Diagram of Timer RD Interrupt.
As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit,
bits ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a
combination of multiple interrupt request sources, the following differences from other maskable interrupts
apply:
• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (interrupt
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the TRDSRi
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set
enabled), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
register, or both of them, are set to 0, the IR bit is set to 0 (no interrupt requested). Therefore, even though the
interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained.
determined by the TRDSRi register.
each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions of
the registers used in different modes (20.3.11, 20.4.14, 20.5.12, 20.6.10, 20.7.10, and 20.8.11).
Timer RD Interrupt
Registers Associated with Timer RD Interrupt
Block Diagram of Timer RD Interrupt
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIERi register
TRDSR0
TRDSR1
OVIE bit
UDF bit
OVF bit
Timer RDi
Status Register
IMIEC bit
IMIED bit
Oct 30, 2009
IMIEA bit
IMIEB bit
IMFA bit
IMFB bit
IMFC bit
IMFD bit
Timer RD
TRDIER0
TRDIER1
Interrupt Enable Register
Timer RD
Timer RDi interrupt request
(IR bit in TRDiIC register)
TRD0IC
TRD1IC
Interrupt Control Register
Timer RD
20. Timer RD