R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 809

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 772 of 802
35.14 Notes on Serial Interface (UART2)
35.14.1 Clock Synchronous Serial I/O Mode
35.14.1.1 Transmission/Reception
35.14.1.2 Transmission
35.14.1.3 Reception
When the RTS function is used with an external clock, the RTS2 pin outputs a low-level signal, which informs
the transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high-level signal
when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by
connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an
internal clock is selected.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1
(transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).
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In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2-
associated registers for transmission even if the MCU is used for reception only. Dummy data is output from the
TXD2 pin during reception.
When an internal clock is selected, the shift clock is generated by setting the TE bit in the U2C1 register to 1
(transmission enabled) and setting dummy data in the U2TB register. When an external clock is selected, the
shift clock is generated by setting the TE bit to 1 (transmission enabled), setting dummy data in the U2TB
register, and inputting an external clock.
If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data
in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the OER bit in
the U2RB register is set to 1 (overrun error). At this time, the U2RB register value is undefined. If an overrun
error occurs, the IR bit in the S2RIC register remains unchanged.
To receive data consecutively, set dummy data in the low-order byte in the U2TB register per each receive
operation.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1.
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The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data in the U2TB register).
If the CTS function is selected, input to the CTS2 pin is low.
The RE bit in the U2C1 register is set to 1 (reception enabled).
The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data in the U2TB register).
Oct 30, 2009
35. Usage Notes