R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 588

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 551 of 802
26.2.3
Note:
26.2.4
Note:
b15 to b0
1. Do not write to bits BS0 to BS3 during the SSU operation. Write to these bits when the RE bit in the SSER
Bits BS0 to BS3 (SSU Data Transfer Length Set Bit)
1. When the SSU data transfer length is set to 9 bits or more with the SSBR register, access the SSTDR register in
After Reset
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 0193h
Address 0195h to 0194h
register is set to 0 (reception disabled) and the TE bit is set to 0 (transmission disabled).
To set the SSBR register, set the RE bit in the SSER register to 0 and the TE bit to 0.
From 8 to 16 bits can be used as the SSU data transfer length.
16-bit units.
Symbol
Symbol
Symbol
Symbol
Bit
Bit
Bit
BS0
BS1
BS2
BS3
SS Bit Counter Register (SSBR)
SS Transmit Data Register (SSTDR)
Symbol
—
—
—
—
—
b15
b7
b7
—
—
—
1
1
1
SSU data transfer length set bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
This register stores transmit data.
When the SSTRSR register is detected as empty, the stored transmit data is transferred
to the SSTRSR register and transmission starts.
When the next transmit data is written to the SSTDR register during the data
transmission from the SSTRSR register, continuous transmission is enabled.
When the MLS bit in the SSMR register is set to 1 (transfer data with LSB first), the MSB-
LSB inverted data is read after writing to the SSTDR register.
b14
b6
b6
—
—
—
1
1
1
Oct 30, 2009
Bit Name
b13
b5
—
b5
—
—
1
1
1
b12
b4
b4
—
—
—
1
1
1
(1)
(1)
b3 b2 b1 b0
0 0 0 0: 16 bits
1 0 0 0: 8 bits
1 0 0 1: 9 bits
1 0 1 0: 10 bits
1 0 1 1: 11 bits
1 1 0 0: 12 bits
1 1 0 1: 13 bits
1 1 1 0: 14 bits
1 1 1 1: 15 bits
BS3
b11
b3
b3
—
—
Function
1
1
1
26. Synchronous Serial Communication Unit (SSU)
BS2
b10
b2
b2
—
—
0
1
1
Function
BS1
b1
b1
b9
—
—
0
1
1
BS0
b0
b0
b8
—
—
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—