R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 531

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 494 of 802
Figure 23.6
• Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)
• Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits)
UiC1 register
UiC1 register
UiC0 register
SiTIC register
TXEPT bit in
SiTIC register
UiC1 register
UiC0 register
Transfer clock
UiC1 register
TXEPT bit in
Transfer clock
TE bit in
TI bit in
TE bit in
IR bit in
TI bit in
IR bit in
TXDi
TXDi
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The above applies under the following conditions:
The above applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (one stop bit)
• UiIRS bit in UiC1 register = 1
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (two stop bits)
• UiIRS bit in UiC1 register = 0
(interrupt request generation when transmission is completed)
(interrupt request generation when the transmit buffer is empty)
Transmit Timing in UART Mode
Data set in UiTB register
Start
Start
Data set in UiTB register
bit
bit
ST
ST
Data transfer from UiTB register to
UARTi transmit register
Data transfer from UiTB register to
UARTi transmit register
D0
D0
D1
D1
TC
TC
D2
D2
Oct 30, 2009
D3
D3
Set to 0 when an interrupt request is acknowledged or by a program.
D4
D4
D5
D5
D6
D6
D7
D7 D8
Parity
bit
P
Stop
Stop
SP
bit
bit
SP SP
Stop
bit
ST
ST
D0
Set to 0 when an interrupt request is acknowledged or by a program.
D1
D0 D1
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
D2
fj: Frequency of UiBRG count source (f1, f8, f32, fC)
fEXT: Frequency of UiBRG count source (external clock)
n: Value set in UiBRG register
i = 0 or 1
fj: Frequency of UiBRG count source (f1, f8, f32, fC)
fEXT: Frequency of UiBRG count source (external clock)
n: Value set in UiBRG register
i = 0 or 1
D2 D3
D3
D4
23. Serial Interface (UARTi (i = 0 or 1))
D4
D5
D5
D6
D7
D6
Pulsing stops because TE bit is set to 0.
D7
P
D8
SP
SP SP
ST
D0 D1
ST
D0
D1