R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 584

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 547 of 802
26. Synchronous Serial Communication Unit (SSU)
The synchronous serial communication unit (SSU) supports clock synchronous serial data communication.
26.1
Table 26.1
Note:
Transfer data format
Operating modes
Master/slave device
I/O pins
Transfer clocks
Receive error detection • Overrun error
Multimaster error
detection
Interrupt requests
Selectable functions
Table 26.1 shows the Synchronous Serial Communication Unit Specifications. Figure 26.1 shows a Block Diagram
of Synchronous Serial Communication Unit.
1. All sources use a single interrupt vector table for the synchronous serial communication unit.
Introduction
Item
Synchronous Serial Communication Unit Specifications
• Transfer data length: 8 to 16 bits
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operation as a slave
• When the MSS bit in the SSCRH register is set to 1 (operation as the master
• The clock polarity and the phase of SSCK can be selected.
• Conflict error
5 interrupt requests (transmit end, transmit data empty, receive data full,
overrun error, and conflict error)
• Data transfer direction
• SSCK clock polarity
• SSCK clock phase
device), an external clock is selected (input from the SSCK pin).
device), an internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from the SSCK pin) is selected.
Continuous transmission and reception of serial data are enabled since both
transmitter and receiver have buffer structures.
An overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when the next serial data reception is completed, the ORER bit is set to 1.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operation as the master device) and when starting a serial communication,
the CE bit in the SSSR register is set to 1 if a low-level signal applies to the
SCS pin input. When the SSUMS bit in the SSMR2 register is set to 1 (4-wire
bus communication mode), the MSS bit in the SSCRH register is set to 0
(operation as a slave device) and the SCS pin input changes state from low
to high, the CE bit in the SSSR register is set to 1.
Selectable MSB first or LSB first
Selectable a low or high level when the clock stops
Selectable edges for data change and data download
Oct 30, 2009
26. Synchronous Serial Communication Unit (SSU)
(1)
Specification
.