R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 622

MCU FLASH 96+4KB 100LQFP

R5F2L3AAANFP#U1

Manufacturer Part Number
R5F2L3AAANFP#U1
Description
MCU FLASH 96+4KB 100LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet

Specifications of R5F2L3AAANFP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F2L3AAANFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 585 of 802
27.2.7
Notes:
1. When rewriting the SDAO bit, write 0 to the SDAOP bit simultaneously using the MOV instruction.
2. Do not write to the SDAO bit during a transfer operation.
3. Enabled in master mode. When writing to the BBSY bit, write 0 to the SCP bit simultaneously using the MOV
4. Disabled when the clock synchronous serial format is used.
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0199h
instruction. Execute the same way when a start condition is regenerated.
Symbol
SDAOP SDAO write protect bit
Symbol
IICRST I
SDAO
Bit
SCLO
BBSY
SCP
IIC bus Control Register 2 (ICCR2)
BBSY
b7
0
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
SCL monitor flag
SDA output value control bit
Start/stop condition generation
disable bit
Bus busy bit
2
C bus control block reset bit
SCP
b6
1
Bit Name
Oct 30, 2009
(4)
SDAO
b5
1
SDAOP
b4
1
When hang-up occurs due to communication failure during
the I
block of the I
initializing registers.
0: SCL pin is set to low
1: SCL pin is set to high
When rewriting the SDAO bit, write 0 simultaneously
When read, the content is 1.
When read
0: SDA pin output is held low
1: SDA pin output is held high
When written
0: SDA pin output is changed to low
1: SDA pin output is changed to high-impedance
When writing to the to BBSY bit, write 0 simultaneously
When read, the content is 1.
Writing 1 is invalid.
When read:
0: Bus is released
1: Bus is occupied
When written
0: Stop condition generated
1: Start condition generated
(High-level output via an external pull-up resistor)
(SDA signal changes from low to high
(SDA signal changes from high to low
while SCL signal is held high)
while SCL signal is held high)
2
C bus interface operation, writing 1 resets the control
SCLO
b3
1
2
C bus interface without setting ports or
(1, 2)
(3)
:
b2
1
Function
IICRST
b1
0
b0
1
27. I
2
C bus Interface
(1)
.
(3)
.
R/W
R/W
R/W
R/W
R/W
R/W
R

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