R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 604

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 567 of 802
Figure 26.8
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Read receive data in the SSRDR register
Read receive data in the SSRDR register
Mode)
SSCRH register
SSCRH register
SSER register
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Read the ORER bit in the SSSR register
Read the ORER bit in the SSSR register
Read the RDRF bit in the SSSR register
Read the RDRF in the SSSR register
Dummy read the SSRDR register
No
No
Initialization
ORER = 1?
ORER = 1?
RDRF = 1?
RDRF = 1?
received?
Last data
Oct 30, 2009
Start
End
RSSTP bit
RSSTP bit
RE bit
No
No
Yes
No
Yes
0
1
0
Yes
Yes
Yes
processing
Overrun
error
26. Synchronous Serial Communication Unit (SSU)
(3) If a receive error occurs, perform error processing
(6) after reading the ORER bit.
(1) After setting each register in the synchronous serial
(2) Determine whether it is the last 1 byte of data to be
(4) Confirm that the RDRF bit is set to 1.
(5) Before the last 1 byte of data is received,
(7) Confirm that the RDRF bit is set to 1.
Then set the ORER bit to 0.
Transmission/reception cannot be restarted
while the ORER bit is set to 1.
communication unit register, a dummy read from
the SSRDR register is performed and the receive
operation is started.
received. If so, set to stop after the data is received.
If the RDRF bit is set to 1, read the receive data in
the SSRDR register. When the SSRDR register is
read, the RDRF bit is automatically set to 0.
When the receive operation is completed,
set the RSSTP bit to 0 and the RE bit to 0
before reading the last 1 byte of data.
If the SSRDR register is read before setting
the RE bit to 0, the receive operation is
restarted again.
set the RSSTP bit to 1 and stop after the data
is received.