R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 654

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 617 of 802
28.3.2
Notes:
28.3.3
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before switching LIN operation modes, stop the LIN operation (LINE bit = 0) once.
3. Inputs to timer RA and UART0 are disabled immediately after the LINE bit is set to 1 (LIN operation starts).
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0106h
Address 0107h
(Refer to Figure 28.3 Header Field Transmission Flowchart Example (1) and Figure 28.7 Header Field
Reception Flowchart Example (2) .)
Symbol
Symbol
LSTART Synch Break detection start bit
BCDCT Bus collision detection flag
Symbol
RXDSF RXD0 input status flag
Symbol
SFDCT Synch Field measurement-complete
SBDCT Synch Break detection flag
B0CLR SFDCT flag clear bit
B1CLR SBDCT flag clear bit
B2CLR BCDCT flag clear bit
Bit
Bit
SBIE
BCIE
SFIE
LINE
MST
SBE
LIN Control Register (LINCR)
LIN Status Register (LINST)
—
—
LINE
b7
b7
—
0
0
Synch Field measurement-complete
interrupt enable bit
Synch Break detection interrupt
enable bit
Bus collision detection interrupt
enable bit
RXD0 input unmasking timing
select bit
(enabled only in slave mode)
LIN operation mode setting bit
LIN operation start bit
flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
MST
b6
b6
—
0
0
Oct 30, 2009
Bit Name
Bit Name
B2CLR
SBE
b5
b5
0
0
LSTART
B1CLR
b4
b4
(2)
(1)
0
0
0: Synch Field measurement-complete interrupt
1: Synch Field measurement-complete interrupt
0: Synch Break detection interrupt disabled
1: Synch Break detection interrupt enabled
0: Bus collision detection interrupt disabled
1: Bus collision detection interrupt enabled
0: RXD0 input enabled
1: RXD0 input disabled
When 1 is written, timer RA input is enabled and
RXD0 input is disabled.
When read, the content is 0.
0: Unmasked after Synch Break detection
1: Unmasked after Synch Field measurement
0: Slave mode
1: Master mode
0: LIN operation stops
1: LIN operation starts
When this bit is set to 1, Synch Field measurement
is completed.
when this bit is set to 1, Synch Break is detected or
Synch Break generation is completed.
When this bit is set to 1, bus collision is detected.
When 1 is written, the SFDCT bit is set to 0.
When read, the content is 0.
When 1 is written, the SBDCT bit is set to 0.
When read, the content is 0.
When 1 is written, the BCDCT bit is set to 0.
When read, the content is 0.
RXDSF
B0CLR
disabled
enabled
is completed
(Synch Break detection circuit operation)
(timer RA output OR’ed with TXD0)
b3
b3
0
0
BCDCT
BCIE
b2
b2
0
0
Function
SBDCT
Function
(3)
SBIE
b1
b1
0
0
SFDCT
SFIE
b0
b0
0
0
28. Hardware LIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R
R
R