R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 253

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 216 of 802
15.3.10 DTC Activation Source Acknowledgement and Interrupt Source Flags
15.3.10.1 Interrupt Sources Except for Flash Memory, Timer RC, Timer RD, Timer
15.3.10.2 Flash Memory
15.3.10.3 Timer RC, Timer RD
15.3.10.4 SSU/I
15.3.10.5 SSU/I
When the DTC activation source is an interrupt source except for the flash memory, timer RC, timer RD, timer
RG, or the synchronous serial communication unit/I
acknowledged for 8 to 12 cycles of the CPU clock after the interrupt source is generated. If a DTC activation
source is generated during DTC operation and acknowledged, the same DTC activation source cannot be
acknowledged for 8 to 12 cycles of the CPU clock on completion of the DTC transfer immediately before the
DTC is activated by the source.
When the DTC activation source is flash memory ready status, even if a flash memory ready status interrupt
request is generated, it is not acknowledged as the DTC activation source after the RDYSTI bit in the FST
register is set to 1 (flash memory ready status interrupt request) and before the DTC sets the RDYSTI bit to 0
(no flash memory ready status interrupt request). If a flash memory ready status interrupt request is generated
after the DTC sets the RDYSTI bit to 0, the DTC acknowledges it as the activation source. 8 to 12 cycles of the
CPU clock are required after the RDYSTI bit is set to 1 and before the DTC sets the interrupt request flag to 0.
If a flash memory ready status interrupt request is generated during DTC operation and acknowledged as the
DTC activation source, the RDYSTI bit is set to 0 after 8 to 12 cycles of the CPU clock on completion of the
DTC transfer immediately before the DTC is activated by the source.
When the DTC activation source is an interrupt source for timer RC or timer RD, even if an input
capture/compare match in individual timers occurs, it is not acknowledged as the DTC activation source after
the interrupt source flag is set to 1 and before the DTC sets the flag to 0. If an input capture/compare match
occurs after the DTC sets the interrupt source flag to 0, the DTC acknowledges it as the activation source. 8 to
12 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock are required after the interrupt
source flag is set to 1 and before the DTC sets the flag to 0. If individual DTC activation sources are generated
for timer C and timer D during DTC operation and acknowledged, the interrupt source flag is set to 0 after 8 to
12 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock on completion of the DTC
transfer immediately before the DTC is activated by the source.
When the DTC activation source is SSU/I
using a data transfer. The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in
SSRDR/ICDRR register) by reading the SSRDR register/ the ICDRR register. If an interrupt source for receive
data full is subsequently generated, the DTC acknowledges it as the activation source.
When the DTC activation source is SSU/I
register using a data transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not
transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT
register. If an interrupt source for transmit data empty is subsequently generated, the DTC acknowledges it as
the activation source.
RG, and Synchronous Serial Communication Unit (SSU)/I
2
2
C bus Receive Data Full
C bus Transmit Data Empty
Oct 30, 2009
2
2
C bus receive data full, read the SSRDR register/the ICDRR register
C bus transmit data empty, write to the SSTDR register/the ICDRT
2
C bus, the same DTC activation source cannot be
2
C bus
15. DTC