R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 342

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 305 of 802
Figure 19.19
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
TSTART bit in
• TRCGRB register setting value greater than
TRCGRA register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC register,
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
IMFC bit in
IMFA bit in
IMFB bit in
low-level output at compare match with the TRCGRB register).
TRC register value
0000h
Operating Example in PWM2 Mode (Duty 0% and Duty 100%)
1
0
1
0
1
0
1
0
m
n
p
“L” initial
output
m+1
p+1
“H” output at TRCGRC register
compare match
Oct 30, 2009
Set to 0 by a
program.
No compare match with
TRCGRB register, so
“H” output continues.
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
TSTART bit in
• TRCGRC register setting value greater than
TRCGRA register setting value
IMFA bit in
IMFB bit in
IMFC bit in
m: Value set in TRCGRA register
n: Value set in TRCGRB register
p: Value set in TRCGRC register
TRC register value
0000h
1
0
1
0
1
0
1
0
No compare match
with TRCGRC register,
so “L” output continues.
p
m
n
“L” initial
output
m+1
n+1
“L” output at
TRCGRB register
compare match
(i.e. no change)
19. Timer RC