R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 796

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 759 of 802
35.8
35.8.1
35.8.2
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Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count
starts.
Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time in the MCU.
Consequently, the timer value may be updated during the period when these two registers are being read.
In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the
TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR register to 1 (one-
shot stops), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot
generation mode and programmable wait one-shot generation mode, read the timer count value before the timer
stops.
The TCSTF bit remains 0 (count stops) for one or two cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB
counting at the first active edge of the count source after the TCSTF bit is set to 1 (during count operation).
The TCSTF bit remains 1 for one or two cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB
Note:
When the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
When 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. When 1 is written to the TOSSP bit during the period
between when 1 is written to the TOSST bit and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to
either 0 or 1 depending on the content state. Likewise, when 1 is written to the TOSST bit during the period
between when 1 is written to the TOSSP bit and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to
either 0 or 1.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following:
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To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following:
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1. Registers associated with timer RB:
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for
each write interval.
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for
each write interval.
Notes on Timer RB
TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR
Timer Mode
Programmable Waveform Generation Mode
Oct 30, 2009
(1)
(1)
other than the TCSTF bit.
other than the TCSTF bit. Timer RB starts
35. Usage Notes