R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 749

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 712 of 802
33.4.11.4 Block Erase Command
When 20h is written in the first bus cycle and then D0h is written in the second bus cycle to any block address,
auto-erasure (erase and erase verify operation) starts in the specified block.
The FST7 bit in the FST register can be used to confirm whether auto-erasure has completed. The FST7 bit is
set to 0 during auto-erasure and is set to 1 when auto-erasure completes. After auto-erasure completes, all data
in the block is set to FFh.
After auto-erasure has completed, the auto-erase result can be confirmed by the FST5 bit in the FST register.
(Refer to 33.4.12 Full Status Check).
The block erase command targeting each block in the program ROM can be disabled using the lock bit.
The following commands are not accepted under the following conditions:
•
•
•
•
Figure 33.9 shows the Block Erase Flowchart (Flash Ready Status Interrupt Disabled), Figure 33.10 shows the
Block Erase Flowchart (Flash Ready Status Interrupt Disabled and Suspend Enabled), and Figure 33.11 shows
the Block Erase Flowchart (Flash Ready Status Interrupt Enabled and Suspend Enabled).
In EW1 mode, do not execute this command to any block where a rewrite control program is allocated.
While the RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled), a flash ready
status interrupt can be generated upon completion of auto-erasure. While the RDYSTIE bit is set to 1 and the
FMR20 bit in the FMR2 register is set to 1 (erase-suspend enabled), a flash ready status interrupt is generated
when the FMR21 bit is set to 1 (erase-suspend request) and auto-erasure suspends. The auto-erase result can be
confirmed by reading the FST register during the interrupt routine.
Block erase commands targeting data flash block A when the FMR14 bit in the FMR1 register is set to 1
(rewrite disabled).
Block erase commands targeting data flash block B when the FMR15 bit is set to 1 (rewrite disabled).
Block erase commands targeting data flash block C when the FMR16 bit is set to 1 (rewrite disabled).
Block erase commands targeting data flash block D when the FMR17 bit is set to 1 (rewrite disabled).
Oct 30, 2009
33. Flash Memory