R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 350

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 313 of 802
Figure 20.5
20.2.3
• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b.
• Bits CMD1 to CMD0 in the TRDFCR register are set to 00b.
The above applies under the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (TRD0 register is set to 0000h by input capture).
TRD0 register value
TRD1 register value
The TRD1 register is synchronized with the TRD0 register.
• Synchronous preset
• Synchronous clear
The PWM 3 bit in the TRDFCR register is set to 1.
Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (TRD1 register is set to 0000h synchronizing with
the TRD0 register).
When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the
TRD0 and TRD1 registers after writing to the TRDi register.
When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are
set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register is set
to 0000h.
Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi
register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0
register is set to 0000h.
TRDIOA0 input
Synchronous Operation
Synchronous Operation
n
n
Oct 30, 2009
n writing
n is set.
n is set.
0000h is set synchronizing with the TRD0 register.
0000h is set by input capture.
(Input capture at the rising edge of the TRDIOA0 input)
20. Timer RD