R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 24

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.
28.
27.1
27.2
27.3
27.4
27.5
27.6
27.7
27.8
27.9
28.1
28.2
28.3
28.4
28.5
28.6
27.2.1
27.2.2
27.2.3
27.2.4
27.2.5
27.2.6
27.2.7
27.2.8
27.2.9
27.2.10 IIC bus Status Register (ICSR) ......................................................................................................... 588
27.2.11 Slave Address Register (SAR) .......................................................................................................... 589
27.2.12 IIC bus Shift Register (ICDRS) ........................................................................................................ 589
27.3.1
27.3.2
27.3.3
27.4.1
27.4.2
27.4.3
27.4.4
27.4.5
27.5.1
27.5.2
27.5.3
28.3.1
28.3.2
28.3.3
28.4.1
28.4.2
28.4.3
28.4.4
I
Hardware LIN .............................................................................................................................. 615
2
C bus Interface ......................................................................................................................... 578
Introduction ........................................................................................................................................... 578
Registers ................................................................................................................................................ 581
Common Items for Multiple Modes ...................................................................................................... 590
I
Clock Synchronous Serial Mode ........................................................................................................... 605
Register Setting Examples ..................................................................................................................... 608
Noise Canceller ..................................................................................................................................... 612
Bit Synchronization Circuit ................................................................................................................... 613
Notes on I
Introduction ........................................................................................................................................... 615
Input/Output Pins .................................................................................................................................. 616
Registers ................................................................................................................................................ 616
Functional Description .......................................................................................................................... 618
Interrupt Requests .................................................................................................................................. 627
Notes on Hardware LIN ........................................................................................................................ 628
2
C bus Interface Mode ......................................................................................................................... 594
Module Standby Control Register (MSTCR) ................................................................................... 581
SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 581
I/O Function Pin Select Register (PINSR) ....................................................................................... 582
IIC bus Transmit Data Register (ICDRT) ......................................................................................... 583
IIC bus Receive Data Register (ICDRR) .......................................................................................... 583
IIC bus Control Register 1 (ICCR1) ................................................................................................. 584
IIC bus Control Register 2 (ICCR2) ................................................................................................. 585
IIC bus Mode Register (ICMR) ........................................................................................................ 586
IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 587
Transfer Clock .................................................................................................................................. 590
SDA Pin Digital Delay Selection ...................................................................................................... 592
Interrupt Requests ............................................................................................................................. 593
I
Master Transmit Operation ............................................................................................................... 595
Master Receive Operation ................................................................................................................ 597
Slave Transmit Operation ................................................................................................................. 600
Slave Receive Operation ................................................................................................................... 603
Clock Synchronous Serial Format .................................................................................................... 605
Transmit Operation ........................................................................................................................... 606
Receive Operation ............................................................................................................................. 607
LIN Control Register 2 (LINCR2) .................................................................................................... 616
LIN Control Register (LINCR) ......................................................................................................... 617
LIN Status Register (LINST) ............................................................................................................ 617
Master Mode ..................................................................................................................................... 618
Slave Mode ....................................................................................................................................... 621
Bus Collision Detection Function ..................................................................................................... 625
Hardware LIN End Processing ......................................................................................................... 626
2
C bus Format .................................................................................................................................. 594
2
C bus Interface .................................................................................................................... 614
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