R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 195

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 158 of 802
Figure 11.4
11.3.5
11.3.6
Table 11.5
Watchdog timer, oscillation stop detection, address break
Software, address match, single-step
Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an
interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt
response time includes the period from when an interrupt request is generated until the currently executing
instruction is completed (refer to (a) in Figure 11.4) and the period required for executing the interrupt sequence
(20 cycles, refer to (b) in Figure 11.4).
When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt
is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 11.5 is set in
the IPL.
Table 11.5 lists the IPL Value When Software or Special Interrupt is Acknowledged.
Interrupt request generation
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
IPL Value When Software or Special Interrupt is Acknowledged
Interrupt Response Time
(a) The period from when an interrupt request is generated until the currently executing instruction is completed.
(b) 21 cycles for address match and single-step interrupts.
The length of time varies depending on the instruction being executed. The DIVX instruction requires
the longest time, 30 cycles (no wait states if the divisor is a register).
Interrupt Source without Interrupt Priority Level
Instruction
(a)
Oct 30, 2009
Interrupt response time
Interrupt request acknowledgement
Interrupt sequence
20 cycles (b)
interrupt routine
Instruction in
7
No change
Time
Value Set in IPL
11. Interrupts