R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 858

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Renesas Technology Corp.
Applicable
Please note the following when using timer RG for the above applicable products.
1.
(c) 2009. Renesas Technology Corp., All rights reserved.
Category
Product
Product
Title
Notes on timer RG
(1) When writing to the TRG register or TRGCR register, make sure the TSTART bit in the TRGMR register to 0 (count
(2) When setting bits IMFA, IMFB, UDF, or OVF in the TRGSR register to 0, use the MOV instruction to ensure that only
(3) When reading the TRGSR register after writing to it, insert one or more NOP instructions between the instructions
(4) When using the output compare function in timer mode, use the TRGIOR register to select the compare match
(5) When using PWM mode, the TRGIOA pin becomes the PWM output pin by setting the PWM bit in the TRGMR
stops).
the specified bits are written to 0 and the other bits are written to 1. Write 0Fh to this register immediately after
writing to these bits. Do not generate an interrupt or a DTC transfer until 0Fh is written.
used for writing and reading.
output from the following three: low-level output, high-level output, or toggle output. When waveform output mode is
selected, the port functions as the compare match output pin (TRGIOA or TRGIOB) while the TRGIOASEL bit or the
TRGIOBSEL bit in the TIMSR register
IOA1, or bits IOB0 and IOB1 in the TRGIOR register until the first compare match occurs.
After setting the TRGIOR register, the output level is undefined for one cycle of the timer RG operating clock, and the
corresponding level to bits IOA0 and IOA1 or bits IOB0 and IOB1 is output.
register to 1 (PWM mode) while the TRGIOASEL bit in the TIMSR register
output pin depends on the settings of bits CCLR0 and CCLR1 in the TRGCR register until the first compare match
occurs.
After setting the PWM bit, the output level is undefined for one cycle of the timer RG operating clock, and the
corresponding level to bits CCLR0 and CCLR1 is output.
Note:
Note:
1. These bits apply to the R8C/36A Group and R8C/38A Group. In the R8C/Lx Series, this condition applies
1. This bit applies to the R8C/36A Group and R8C/38A Group. In the R8C/Lx Series, this condition applies to
MPU/MCU
Notes on Timer RG
R8C/36A Group, R8C/38A Group,
R8C/Lx Series
to the TRGIOASEL0 bit or the TRGIOBSEL0 bit in the TRGPSR register.
the TRGIOASEL0 bit in the TRGPSR register.
RENESAS TECHNICAL UPDATE
(1)
is 1. The output level of these pins depend on the settings of bits IOA0 and
Lot No.
Information
Reference
Document
Document
Category
No.
(1)
TN-R8C-A006A/E
Technical Notification
is 1. The output level of the PWM
Date: Sep.25, 2009
Rev.
Page 1 of 2
1.00