R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 559

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 522 of 802
Figure 24.7
(1) Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)
(2) Transmit Timing Example When Transfer Data 9 Bits is Long (Parity Disabled, Two Stop Bits)
Transfer clock
Transfer clock
S2TIC register
S2TIC register
U2C1 register
U2C1 register
U2C1 register
U2C0 register
The above applies under the following conditions:
U2C1 register
U2C0 register
The above applies under the following conditions:
TXEPT bit in
TXEPT bit in
• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 1 (two stop bits)
• CRD bit in U2C0 register = 1 (CTS/RTS function disabled)
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the transmit buffer is empty)
• PRYE bit in U2MR register = 1 (parity enabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• U2IRS bit in U2C1 register = 1 (interrupt request generation when transmission is completed)
TE bit in
TE bit in
IR bit in
TI bit in
IR bit in
TI bit in
CTS2
TXD2
TXD2
1
0
1
0
1
0
1
0
“H”
“L”
Transmit Timing in UART Mode
1
0
1
0
1
0
1
0
Start
ST
Data set in U2TB register
bit
D0
Start
ST
bit
Set to 0 when an interrupt request is acknowledged or by a program.
D1
D0
Oct 30, 2009
Data set in U2TB register
D2
D1
TC
D3
D2
TC
D4
D3
D5
D4
The transfer clock stops once because the CTS pin is “H” when the stop bit is verified.
The transfer clock resumes running immediately after the CTS pin is verified to be “L”.
D6
D5
D7
D6
D8
D7
Stop
Parity
SP
bit
P
bit
SP
SP
Set to 0 when an interrupt request is acknowledged or by a program.
Stop
Stop
bit
bit
Data transfer from U2TB register to
UART2 transmit register
Data transfer from U2TB register to
UART2 transmit register
ST
ST
D0
D0
D1
D1
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
fj: Frequency of U2BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U2BRG count source (external clock)
n: Value set in U2BRG register
D2
D2
fj: Frequency of U2BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U2BRG count source (external clock)
n: Value set in U2BRG register
D3
D3
D4
D4
Pulsing stops because TE bit is set to 0.
D5
D5
D6
D6
24. Serial Interface (UART2)
D7
D7
D8
P
SP
SP SP
ST
ST
D0
D0
D1
D1