R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 248

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 211 of 802
Figure 15.8
15.3.4
Table 15.6
j =0 to 23
DTC block size register j
DTC transfer count register j
DTC transfer count reload
register j
DTC source address register j
DTC destination address
register j
One to 256 bytes of data are transferred by one activation. The number of transfer times can be 1 to 256. When
the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed, an interrupt
request for the CPU is generated during DTC operation.
Table 15.6 shows Register Functions in Normal Mode.
Figure 15.8 shows Data Transfers in Normal Mode.
X: 0 or 1
DTCCR register
Bits b3 to b0 in
Normal Mode
Register
00X0b
01X0b
10X0b
11X0b
Data Transfers in Normal Mode
Register Functions in Normal Mode
Transfer source
SRC
Source address
Incremented
Incremented
control
Fixed
Fixed
Oct 30, 2009
DTBLSj
DTCCTj
DTRLDj
DTSARj
DTDARj
Symbol
Destination address
Transfer
Incremented
Incremented
control
Fixed
Fixed
Transfer destination
Size of the data block to be transferred by one activation
Number of times of data transfers
Not used
Data transfer source address
Data transfer destination address
DST
Source address
after transfer
SRC+N
SRC+N
SRC
SRC
Size of the data block to be transferred
by one activation (N bytes)
DTBLSj = N
DTSARj = SRC
DTDARj = DST
j = 0 to 23
Function
Destination address
after transfer
DST+N
DST+N
DST
DST
15. DTC