R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 650

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 613 of 802
27.8
Figure 27.21
Table 27.7
1Tcyc = 1/f1(s)
When the I
•
•
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 27.21 shows the Bit Synchronization Circuit Timing and Table 27.7 lists the Time between Changing SCL
Signal from Low-Level Output to High-Impedance and Monitoring SCL Signal.
The SCL signal is held low by a slave device.
The rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Bit Synchronization Circuit
CKS3
2
C bus interface is set to master mode, the high-level period may become shorter if:
0
1
Bit Synchronization Circuit Timing
Monitoring SCL Signal
Time between Changing SCL Signal from Low-Level Output to High-Impedance and
ICCR1 Register
SCL monitor timing
Reference clock of
Internal SCL
Oct 30, 2009
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
SCL Monitoring Time
27. I
2
C bus Interface