R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 336

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 299 of 802
Table 19.13
j = A, B, or C
Count source
Count operation
PWM waveform
Count start conditions
Count stop conditions
Interrupt request
generation timing
TRCIOA/TRCTRG pins
function
TRCIOB pin function
TRCIOC/TRCIOD pins
function
INT0 pin function
Read from timer
Write to timer
Selectable functions
Item
PWM2 Mode Specifications
f1, f2, f4, f8, f32, or
external signal input to TRCCLK pin (rising edge)
TRC register increment
PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in
• The count stops at a compare match with TRCGRA while the CSEL bit in the TRCCR2
• Compare match (the contents of the TRC register and the TRCGRj register match.)
• TRC register overflow
Programmable I/O port or TRCTRG input
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• External trigger and active edge selection
• Buffer operation (Refer to 19.3.2 Buffer Operation .)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse
• Digital filter (Refer to 19.3.3 Digital Filter .)
• A/D trigger generation
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).
A trigger is input to the TRCTRG pin.
the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in
the TRCCR1 register. The TRC register retains the value before the count stops.
register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before the
count stops when the CCLR bit in the TRCCR1 register is set to 0. The TRC register is
set to 0000h when the CCLR bit in the TRCCR1 register is set to 1.
The edge or edges of the signal input to the TRCTRG pin can be used as the PWM
output trigger: rising edge, falling edge, or both rising and falling edges
Output .)
fk: Frequency of count source
m: Value set in TRCGRA register
n: Value set in TRCGRB register
p: Value set in TRCGRC register
Oct 30, 2009
TRCIOB output
TRCTRG input
m+1
n+1
p+1
n-p
Specification
(TRCTRG: Rising edge, active level is high)
n+1
p+1
n-p
19. Timer RC