R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 500

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 463 of 802
22.5
Table 22.7
j = A or B
Count sources
Count operation
Count periods
Waveform output timing
Count start condition
Count stop condition
Interrupt request generation
timing
TRGIOA/TRGIOB
pins function
TRGCLKA/TRGCLKB
pins function
Read from timer
Write to timer
Selectable functions
This mode (output compare function) detects when the contents of the TRG register and the TRGGRA or
TRGGRB register match (compare match). When a match occurs, a signal is output from the TRGIOA or TRGIOB
pin at a given level.
Table 22.7 lists the Output Compare Function Specifications.
Timer Mode (Output Compare Function)
Item
Output Compare Function Specifications
Oct 30, 2009
f1, f4, f8, f32, or
1 (count starts) is written to the TSTART bit in the TRGMR register.
The count value can be read by reading the TRG register.
The TRG register can be written to.
external signal input to the TRGCLKj pin (active edge selectable by a
program)
Increment
• When bits CCLR1 to CCLR0 in the TRGCR register are set to 00b
• When bits CCLR1 to CCLR01 in the TRGCR register are set to 01b or
Compare match
0 (count stops) is written to the TSTART bit in the TRGMR register.
• Compare match (the contents of the TRG register and the TRGGRj
• TRG register overflow
Programmable I/O port or output-compare output
(selectable for each individual pin)
Programmable I/O port or external clock input
• Output-compare output pin selection
• Output level selection at compare match
• Timing for setting the TRG register to 0000h
• Buffer operation (Refer to 22.3.2 Buffer Operation .)
1/fk × 65,536 fk: Frequency of count source
(free-running operation)
10b (TRG is set to 0000h by a compare match with TRGGRj)
1/fk × (n+1)
n: Value set in TRGGRj register
register match)
Either one or both of pins TRGIOA and TRGIOB
Low-level output, high-level output, or inverted output level
Overflow or compare match with the TRGGRj register
Specification
22. Timer RG