R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 245

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 208 of 802
Figure 15.3
Figure 15.4
Write 0 to the interrupt source
flag in the status register
Write back control data
Write back control data
DTC activation source
DTC activation source
Read control data
Read control data
Read DTC vector
Read DTC vector
Transfer data
Transfer data
generation
NMIF = 1?
generation
CHNE=1?
NMIF = 1?
CHNE=1?
Branch 1
Branch 1
End
End
No
No
No
No
Timer RC, Timer RD, Timer RG, or Flash Memory Interrupt Source
RD, or Timer RG Interrupt Source
DTC Internal Operation Flowchart When DTC Activation Source is not SSU/I
DTC Internal Operation Flowchart When DTC Activation Source is Timer RC, Timer
Yes
Yes
Yes
Yes
Oct 30, 2009
Write back control data
Write back control data
Read control data
Read control data
Transfer data
Transfer data
CHNE=1?
CHNE=1?
No
No
Yes
Yes
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated
when transfer is either of the following:
- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated
when transfer is either of the following:
- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) register
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) register
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
repeat mode
repeat mode
Generate an interrupt request
Generate an interrupt request
Write 0 to the bit among
Write 0 to the bit among
Write back control data
Write back control data
DTCENi0 to DTCENi7
DTCENi0 to DTCENi7
Interrupt handling
Interrupt handling
Transfer data
Transfer data
for the CPU
for the CPU
CHNE=1?
CHNE=1?
No
No
Yes
Yes
Write back control data
Write back control data
Read control data
Read control data
Transfer data
Transfer data
CHNE=1?
CHNE=1?
No
No
Yes
Yes
2
C bus,
15. DTC