R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 370

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 333 of 802
Table 20.7
i = 0 or 1, j = either A, B, C, or D
Count sources
Count operations
Count period
Waveform output timing
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pins function
INT0 pin function
Read from timer
Write to timer
Selectable functions
Item
Output Compare Function Specifications
Oct 30, 2009
f1, f2, f4, f8, f32, fC2, or
external signal input to the TRDCLK pin (active edge selectable by a program)
Increment
• When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running
• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (TRDi register is
Compare match
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
• Compare match (the contents of the TRDi register and the TRDGRji register
• TRDi register overflow
Programmable I/O port, output-compare output, or TRDCLK (external clock) input
Programmable I/O port or output-compare output (selectable for each individual pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRDi register.
• When the SYNC bit in the TRDMR register is set to 0 (timer RD0 and timer RD1
• When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1
• Output-compare output pin selection
• Output level selection at the compare match
• Initial output level selected
• Timing for setting the TRDi register to 0000h
• Buffer operation (Refer to 20.2.2 Buffer Operation. )
• Synchronous operation (Refer to 20.2.3 Synchronous Operation. )
• Changing output pins for registers TRDGRCi and TRDGRDi
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse Output Forced
• Timer RD can be used as the internal timer without output.
• A/D trigger generation
operation)
1/fk × 65,536 fk: Frequency of count source
set to 0000h at compare match with the TRDGRji register).
Frequency of count source x (n+1)
n: Value set in TRDGRji register
CSELi bit in the TRDSTR register is set to 1.
The output compare output pin holds output level before the count stops.
compare match with the TRDGRAi register.
The output compare output pin holds the level after the output changes by the
compare match.
match.)
operate independently).
Data can be written to the TRDi register.
operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Either one or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
Low-level output, high-level output, or output level inversion
Selectable level for the period from the count start to the compare match
Overflow or compare match with the TRDGRAi register
The TRDGRCi register can be used as output control of the TRDIOAi pin and the
TRDGRDi register can be used as output control of the TRDIOBi pin.
Cutoff. )
Specification
20. Timer RD