R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 671

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 634 of 802
29.2.4
Table 29.2
Bits CH2 to CH0
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00D5h
If the content of the ADINSEL register is rewritten during A/D conversion, the conversion result is undefined.
Symbol ADGSEL1 ADGSEL0 SCAN1
000b
001b
010b
100b
101b
011b
110b
111b
ADGSEL0 A/D input group select bit
ADGSEL1
Symbol
SCAN0 A/D sweep pin count select bit
SCAN1
Bit
CH0
CH1
CH2
A/D Input Select Register (ADINSEL)
—
Analog Input Pin Selection
b7
1
Analog input pin select bit
Reserved bit
Bits ADGSEL1 to
ADGSEL0 = 00b
b6
1
Bit Name
Oct 30, 2009
AN0
AN1
AN3
AN4
AN5
AN6
AN2
AN7
b5
0
SCAN0
b4
0
Refer to Table 29.2 Analog Input Pin Selection
Set to 0.
b5 b4
b7 b6
0 0: 2 pins
0 1: 4 pins
1 0: 6 pins
1 1: 8 pins
0 0: Port P13_0 to P13_3 and port P0_0 to P0_3
0 1: Port P0_4 to P0_7 and port P1_0 to P1_3
1 0: Port P13_4 to P13_7 group selected
1 1: Port group not selected
groups selected
groups selected
Bits ADGSEL1 to
ADGSEL0 = 01b
b3
—
0
AN10
AN12
AN13
AN14
AN15
AN11
AN8
AN9
CH2
b2
0
Function
CH1
b1
0
Bits ADGSEL1 to
ADGSEL0 = 10b
CH0
b0
0
Do not set.
AN16
AN17
AN18
AN19
29. A/D Converter
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W