R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 509

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 472 of 802
Figure 22.16
22.7.1
22.7.2
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0172h
Figure 22.16 shows a Procedure Example for Setting Phase Counting Mode.
Symbol
Symbol
CKEG0 External clock active edge
CKEG1
CCLR0
CCLR1
Bit
TCK0
TCK1
TCK2
Timer RG Control Register (TRGCR) in Phase Counting Mode
Procedure Example for Setting Phase Counting Mode
Select phase counting mode
—
Count operation starts
Phase counting mode
Phase counting mode
Procedure Example for Setting Phase Counting Mode
b7
—
1
Count source select bit
select bit
TRG register clear select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
CCLR1
b6
0
Bit Name
Oct 30, 2009
CCLR0
b5
0
(1)
(2)
CKEG1
(1) Set the MDF bit in the TRGMR register to 1 to select phase
(2) Set the TSTART bit in the TRGMR register to 1 to start count
b4
0
counting mode.
operation.
Disabled in phase counting mode.
Disabled in phase counting mode.
b6 b5
0 0: Clear disabled
0 1: TRG register cleared by input capture or
1 0: TRG register cleared by input capture or
1 1: Do not set.
compare match with TRGGRA
compare match with TRGGRB
CKEG0
b3
0
TCK2
b2
0
Function
TCK1
b1
0
TCK0
b0
0
22. Timer RG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—