R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 347

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 310 of 802
20.2
Figure 20.2
20.2.1
Table 20.3
i = 0 or 1
f1, f2, f4, f8, f32
fC2
External signal input
to TRDCLK pin
TRDCLK/
TRDIOA0
Count Source
The count source selection method is the same in all modes. However, fC2 cannot be selected in PWM, reset
synchronous PWM, complementary PWM, or PWM3 mode. The external clock cannot be selected in PWM3
mode.
The pulse width of the external clock input to the TRDCLK pin should be set to three or more cycles of the
timer RD operating clock. (See Table 20.1 Timer RD Operating Clocks.)
Common Items for Multiple Modes
Count Sources
STCLK = 1
STCLK = 0
Count Source Selection
Count Source Block Diagram
fC2
f32
f1
f2
f4
f8
The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
Bits TCK2 to TCK0 in the TRDCRi register is set to 101b (TRDCLKi input or fC2)
The ITCLKi bit in the TRDECR register is set to 1 (fC2)
The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b
(count source: external clock).
The active edge is selected by bits CKEG0 and CKEG1 in the TRDCRi register.
The PD2_0 bit in the PD2 register is set to 0 (input mode).
ITCLK0, ITCLK1: Bits in TRDECR register
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register
STCLK: Bit in TRDFCR register
ITCLKi = 0
ITCLKi = 1
Oct 30, 2009
TRDIOA0 I/O or programmable I/O port
CKEG1 to CKEG0
Valid edge
selected
= 011b
= 100b
= 010b
TCK2 to TCK0
= 001b
Selection
= 000b
= 101b
Count source
TRDi register
20. Timer RD