R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 553

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 516 of 802
Figure 24.5
24.3.3
24.3.4
The UFORM bit in the U2C0 register can be used to select the transfer format. Figure 24.5 shows the Transfer
Format.
In continuous receive mode, receive operation is enabled by reading the receive buffer register. If this mode is
selected, writing dummy data to the transmit buffer register is not required to enable receive operation.
However, a dummy reading of the receive buffer register is required when starting transmission.
When the U2RRM bit in the U2C1 register is set to 1 (continuous receive mode), the TI bit in the U2C1 register
is set to 0 (data in the U2TB register) by reading the U2RB register. When the U2RRM bit is set to 1, do not
write dummy data to the U2TB register by a program.
LSB First/MSB First Select Function
Continuous Receive Mode
(1) UFORM Bit in U2C0 Register = 0 (LSB first)
(2) UFORM Bit in U2C0 Register = 1 (MSB first)
The above applies under the following conditions:
Transfer Format
CLK2
TXD2
RXD2
CLK2
TXD2
RXD2
• CKPOL bit in U2C0 register = 0
• U2LCH bit in U2C1 register = 0 (not inverted)
(transmit data output at the falling edge and receive data input
at the rising edge of the transfer clock)
Oct 30, 2009
D7
D0
D0
D7
D6
D1
D1
D6
D5
D2
D2
D5
D4
D3
D3
D4
D3
D4
D3
D4
D2
D5
D5
D2
D6
D6
D1
D1
D7
D7
D0
D0
24. Serial Interface (UART2)