R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 228

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 191 of 802
14.2
14.2.1
Note:
14.2.2
Note:
14.2.3
b7 to b0 Writing 00h and then FFh into this register initializes the watchdog timer.
b7 to b0 A write instruction to this register starts the watchdog timer.
1. The PM12 bit is set to 1 when 1 is written by a program (and remains unchanged even if 0 is written to it).
1. Write the WDTR register during the count operation of the watchdog timer.
After Reset
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Bit
Address 0005h
Address 000Dh
Address 000Eh
This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection
mode enabled).
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register.
Symbol
Symbol
Symbol
Registers
Symbol
The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2
register.
Bit
Bit
Bit
PM12
Processor Mode Register 1 (PM1)
Watchdog Timer Reset Register (WDTR)
Watchdog Timer Start Register (WDTS)
—
—
—
—
—
—
—
b7
b7
b7
—
—
—
X
X
0
(1)
Reserved bits
WDT interrupt/reset switch bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bit
b6
b6
b6
—
—
—
X
X
0
Oct 30, 2009
Bit Name
b5
—
b5
—
b5
—
X
X
0
b4
b4
b4
—
—
—
X
X
0
Set to 0.
0: Watchdog timer interrupt
1: Watchdog timer reset
Set to 0.
Function
Function
b3
b3
b3
—
—
—
0
X
X
PM12
b2
b2
b2
—
—
X
X
0
Function
(1)
b1
b1
b1
—
—
—
X
X
0
b0
b0
b0
—
—
—
X
X
0
14. Watchdog Timer
R/W
R/W
R/W
R/W
R/W
R/W
—
W
W