R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 238

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 201 of 802
15.2.3
Note:
15.2.4
Note:
15.2.5
15.2.6
b7 to b0 This register value is reloaded to the DTCCT register in repeat mode.
b7 to b0 These bits specify the number of times of DTC data transfers.
b15 to b0 These bits specify a transfer destination address for data transfer.
1. When the DTCCT register is set to 00h, the number of transfer times is 256. Each time the DTC is activated, the
1. Set the initial value for the DTCCT register.
b15 to b0
After Reset
After Reset
After Reset
After Reset
After Reset
After Reset
Bit
Bit
Address See Table 15.4 Control Data Allocation Addresses .
Address See Table 15.4 Control Data Allocation Addresses .
Address See Table 15.4 Control Data Allocation Addresses .
Address See Table 15.4 Control Data Allocation Addresses .
Bit
Bit
DTCCT register is decremented by 1.
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
Bit
Bit
Bit
Bit
Bit
Bit
DTC Transfer Count Register j (DTCCTj) (j = 0 to 23)
DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23)
DTC Source Address Register j (DTSARj) (j = 0 to 23)
DTC Destination Register j (DTDARj) (j = 0 to 23)
These bits specify a transfer source address for data transfer.
b15
b15
b7
b7
b7
b7
—
—
—
—
—
—
X
X
X
X
X
X
b14
b14
b6
b6
b6
b6
—
—
—
—
—
—
X
X
X
X
X
X
Oct 30, 2009
b13
b13
b5
—
b5
—
b5
—
—
b5
—
—
X
X
X
X
X
X
Function
Function
Function
Function
b12
b12
b4
b4
b4
b4
—
—
—
—
—
—
X
X
X
X
X
X
b11
b11
b3
b3
b3
b3
—
—
—
—
—
—
X
X
X
X
X
X
b10
b10
b2
b2
b2
b2
—
—
—
—
—
—
X
X
X
X
X
X
b1
b1
b1
b9
b1
b9
—
—
—
—
—
—
X
X
X
X
X
X
0000h to FFFFh
0000h to FFFFh
00h to FFh
Setting Range
Setting Range
00h to FFh
Setting Range
b0
b0
b0
b8
b0
b8
—
—
—
—
—
—
X
Setting Range
X
X
X
X
X
(1)
(1)
15. DTC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W