R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 548

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 511 of 802
24.3
Table 24.2
Notes:
Transfer data format
Transfer clock
Transmission/reception
control
Transmit start conditions
Receive start conditions
Interrupt request generation
timing
Error detection
Selectable functions
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 24.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 24.3 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode.
1. If an external clock is selected, the requirements must be met in either of the following states:
2. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC
- The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output
- The external clock is held low when the CKPOL bit in the U2C0 register is set to 1 (transmit data output
register does not change to 1 (interrupt requested).
Clock Synchronous Serial I/O Mode
at the falling edge and receive data input at the rising edge of the transfer clock)
at the rising edge and receive data input at the falling edge of the transfer clock)
Item
Clock Synchronous Serial I/O Mode Specifications
Oct 30, 2009
Transfer data length: 8 bits
• The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1))
• The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin
Selectable from the CTS function, RTS function, or CTS/RTS function disabled.
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled)
• The TI bit in the U2C1 register is set to 0 (data in the U2TB register)
• If the CTS function is selected, input to the CTS2 pin is low.
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data in the U2TB register).
For transmission, one of the following conditions can be selected.
• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
• The U2IRS bit is set to 1 (transmission completed):
For reception
• When data is transferred from the UART2 receive register to the U2RB register
Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
• Serial data logic switching
fj = f1, f8, f32, fC n = Value set in U2BRG register: 00h to FFh
When data is transferred from the U2TB register to the UART2 transmit register
(at start of transmission).
When data transmission from the UART2 transmit register is completed.
(at completion of reception).
Transfer data I/O can be selected to occur synchronously with the rising or falling
edge of the transfer clock.
Whether data transmission/reception begins with bit 0 or begins with bit 7 can be
selected.
Receive operation is enabled immediately by reading the U2RB register.
This function inverts the logic value of transmit/receive data.
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the 7th bit of the next unit of data.
(2)
Specification
24. Serial Interface (UART2)
(1)
(1)