R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 615

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 578 of 802
27. I
The I
I
27.1
2
Table 27.1
Note:
C bus.
Communication formats • I
I/O pins
Transfer clocks
Receive error detection • Overrun error detection (clock synchronous serial format)
Interrupt sources
Selectable functions
Table 27.1 lists the I
Figure 27.2 shows the External Circuit Connection Example of Pins SCL and SDA. Table 27.2 lists the I
Interface Pin Configuration.
* I
1. All sources use a single interrupt vector table for the I
2
2
2
C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips
C bus is a trademark of Koninklijke Philips Electronics N. V.
C bus Interface
Introduction
Item
I
2
C bus Interface Specifications
2
C bus Interface Specifications. Figure 27.1 shows a Block Diagram of I
• Clock synchronous serial format
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
• When the MST bit in the ICCR1 register is set to 0
• When the MST bit in the ICCR1 register is set to 1
• I
• Clock synchronous serial format ...... 4 sources
• I
• Clock synchronous serial format
• SDA digital delay
2
- Selectable as master/slave device
- Continuous transmit/receive operation (because the shift register, transmit
- Start/stop conditions are automatically generated in master mode.
- Automatic loading of the acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
- Support for direct drive of pins SCL and SDA (N-channel open-drain output)
- Continuous transmit/receive operation (because the shift register, transmit
External clock (input from the SCL pin)
Internal clock selected by bits CKS0 to CKS3 in the ICCR1 register and bits
IICTCTWI and IICTCHALF in the PINSR register (output from the SCL pin)
Indicates an overrun error during reception. When the last bit of the next unit
of data is received while the RDRF bit in the ICSR register is set to 1 (data in
the ICDRR register), the AL bit is set to 1.
2
Transmit data empty (including when slave address matches), transmit end,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection
Transmit data empty, transmit end, receive data full, and overrun error
2
- Selectable output level for the acknowledge signal during reception
- Selectable MSB first or LSB first as the data transfer direction
- Digital delay value for the SDA pin selectable by bits SDADLY0 to
Oct 30, 2009
C bus format
C bus format .................................. 6 sources
C bus format
data register, and receive data register are independent)
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes low and the interface
stands by.)
data register, and receive data register are independent)
SDADLY1 in the PINSR register.
Specification
2
C bus interface.
(1)
(1)
2
C bus interface, and
27. I
2
C bus Interface
2
C bus