R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 493

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 456 of 802
Figure 22.3
22.3.2
Table 22.5
Input capture function
Output compare function Compare match between the TRG
PWM mode
The above applies under the following conditions:
• The BUFA bit in the TRGIOR register is set to 1 (TRGGRC register is used as the buffer register of the TRGGRA register).
• Bits IOA2 to IOA0 in the TRGIOR register are set to 100b (input capture at the rising edge).
The BUFA or BUFB bit in the TRGIOR register can be used to select the TRGGRC or TRGGRD register as the
buffer register of the TRGGRA or TRGGRB register.
• Buffer register of TRGGRA register: TRGGRC register
• Buffer register of TRGGRB register: TRGGRD register
Buffer operation differs depending on the mode.
Table 22.5 lists the Buffer Operation in Each Mode, Figure 22.3 shows the Buffer Operation of Input Capture
Function, and Figure 22.4 shows the Buffer Operation of Output Compare Function.
Function, Mode
TRGGRC register
TRGGRA register
Buffer Operation
TRGIOA input
TRG register
(input capture signal)
Buffer Operation in Each Mode
Buffer Operation of Input Capture Function
(buffer)
TRGIOA input
TRGGRC
register
Input capture signal input
register and the TRGGRA (TRGGRB)
register
Oct 30, 2009
n-1
Transfer Timing
m
TRGGRA
register
n
Transfer
Transfer
m
n
The content of the TRGGRA
(TRGGRB) register is transferred to
the buffer register.
The content of the buffer register is
transferred to the TRGGRA
(TRGGRB) register.
n+1
Transfer Destination Register
TRG
22. Timer RG