R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 175

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 138 of 802
Figure 9.4
9.5.3
(flash memory operates)
Stop mode
(flash memory stops)
Interrupt request generation
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 9.4 shows the Time from Stop Mode to Interrupt Routine Execution.
To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting stop mode.
The clock used immediately before stop mode divided by 8 is used as the CPU clock when the MCU exits stop
mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings
of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled).
FMR0 Register
FMSTP Bit
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for
exiting stop mode to 000b (interrupt disabled).
When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when
an interrupt request is generated and the CPU clock supply starts.
0
1
Exiting Stop Mode
stabilization time
100 s (max.)
Internal power
Time from Stop Mode to Interrupt Routine Execution
T0
Stabilization Time (T0)
Internal Power
100 s (max.)
100 s (max.)
Oscillation time of CPU clock
source used immediately
Oct 30, 2009
before stop mode
T1
Period of system clock
Period of system clock
1 cycle + 60 s (max.)
Activation (T2)
Flash Memory
Time until
1 cycle
activation sequence
Flash memory
Period of CPU clock
T2
Same as above
Supply (T3)
CPU Clock
Time until
2 cycles
restart sequence
CPU clock
T3
Period of CPU clock
Same as above
Sequence (T4)
Interrupt
Time for
20 cycles
Interrupt sequence
T4
The total of T0 to T4 is
the time from wait mode
until an interrupt routine
is executed.
Remarks
9. Power Control