R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 408

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 371 of 802
Table 20.11
j = either A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0 pin function
TRDIOD0 pin function
TRDIOA1 pin function
TRDIOC1 pin function
TRDIOB1 pin function
TRDIOD1 pin function
TRDIOC0 pin function
INT0 pin function
Read from timer
Write to timer
Selectable functions
Reset Synchronous PWM Mode Specifications
Item
Oct 30, 2009
f1, f2, f4, f8, f32, or
external signal input to the TRDCLK pin (active edge selectable by a
program)
The TRD0 register is incremented (TRD1 register is not used).
PWM period
Active level width of normal-phase : 1/fk × (m-n)
Active level width of counter-phase: 1/fk × (n+1)
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• Compare match (the content of the TRD0 register matches the
• TRD0 register overflow
Programmable I/O port or TRDCLK (external clock) input
PWM1 output normal-phase output
PWM1 output counter-phase output
PWM2 output normal-phase output
PWM2 output counter-phase output
PWM3 output normal-phase output
PWM3 output counter-phase output
Output inverted every PWM period
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• The normal-phase and counter-phase active level and initial output
• Buffer operation (Refer to 20.2.2 Buffer Operation .)
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse
• A/D trigger generation
fk: Frequency of count source
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register (PWM1 output),
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds the output level before the count stops
stops at the compare match with the TRDGRA0 register.
The PWM output pin holds the level after the output changes by the
compare match.
contents of registers TRDGRj0, TRDGRA1, and TRDGRB1).
level can be selected individually.
Output Forced Cutoff .)
Counter-phase
Normal-phase
Value set in TRDGRA1 register (PWM2 output),
Value set in TRDGRB1 register (PWM3 output)
n+1
m+1
Specification
: 1/fk × (m+1)
m-n
(Active level is low)
20. Timer RD