R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 591

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 554 of 802
26.2.8
Note:
1. Refer to 26.3.1.1 Association between Transfer Clock Polarity, Phase, and Data for the settings of bits
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ah
CPHS and CPOS.
When the SSUMS bit in the SSMR2 register is set to 0 (clock synchronous communication mode), set the CPHS
bit to 0 and the CPOS bit to 0.
Symbol
Symbol
CPOS
Bit
CPHS
MLS
BC0
BC1
BC2
BC3
SS Mode Register (SSMR)
—
MLS
b7
0
Bit counter 3 to 0
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
SSCK clock phase select bit
SSCK clock polarity select bit
MSB first/LSB first select bit
CPOS
b6
0
Oct 30, 2009
Bit Name
CPHS
b5
0
(1)
(1)
b4
—
1
b3 b2 b1 b0
0: Data change at odd edges
1: Data change at even edges
0: High when clock stops
1: Low when clock stops
0: Transfer data with MSB first
1: Transfer data with LSB first
0 0 0 0: 16 bits left
0 0 0 1: 1 bit left
0 0 1 0: 2 bits left
0 0 1 1: 3 bits left
0 1 0 0: 4 bits left
0 1 0 1: 5 bits left
0 1 1 0: 6 bits left
0 1 1 1: 7 bits left
1 0 0 0: 8 bits left
1 0 0 1: 9 bits left
1 0 1 0: 10 bits left
1 0 1 1: 11 bits left
1 1 0 0: 12 bits left
1 1 0 1: 13 bits left
1 1 1 0: 14 bits left
1 1 1 1: 15 bits left
BC3
b3
(Data download at even edges)
(Data download at odd edges)
0
26. Synchronous Serial Communication Unit (SSU)
BC2
b2
0
Function
BC1
b1
0
BC0
b0
0
R/W
R/W
R/W
R/W
—
R
R
R
R