R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 560

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 523 of 802
Figure 24.8
24.4.1
Table 24.8
Bit Rate
S2RIC register
115200
Receive Timing Example When Transfer Data 8 Bits is Long (Parity Disabled, One Stop Bit)
14400
19200
28800
38400
57600
U2C1 register
U2C1 register
Transfer clock
(bps)
1200
2400
4800
9600
count source
In UART mode, the bit rate is the frequency divided by the U2BRG register divided by 16. Table 24.8 lists the
Bit Rate Setting Example in UART Mode (Internal Clock Selected).
RE bit in
U2BRG
RI bit in
IR bit in
RXD2
RTS2
U2BRG
Source
Count
Bit Rate
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
The above applies under the following conditions:
Receive Timing in UART Mode
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
“H”
“L”
1
0
1
0
1
0
• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS2/RTS2 function enabled), CRS bit = 1 (RTS2 function selected)
129 (81h)
129 (81h)
42 (2Ah)
10 (0Ah)
64 (40h)
32 (20h)
86 (56h)
64 (40h)
32 (20h)
21 (15h)
U2BRG
Setting
Value
System Clock = 20 MHz
Reception starts when a transfer clock
is generated at the falling edge
of the start bit.
Oct 30, 2009
Actual Time
Start bit
113636.36
14367.82
19230.77
29069.77
37878.79
56818.18
(bps)
1201.92
2403.85
4734.85
9615.38
“L” is determined.
Setting
Error
(%)
-1.36 29 (1Dh)
-0.22 79 (4Fh)
-1.36 29 (1Dh)
-1.36 19 (13h)
-1.36
0.16 119 (77h)
0.16 59 (3Bh)
0.16 119 (77h)
0.16 59 (3Bh)
0.94 39 (27h)
U2BRG
9 (09h)
Setting
System Clock = 18.432 MHz
D0
Value
Data transfer from UART2 receive register to
U2RB register
Set to 0 when an interrupt request is acknowledged or by a program.
Received data capture
Actual Time
115200.00
14400.00
19200.00
28800.00
38400.00
57600.00
(bps)
1200.00
2400.00
4800.00
9600.00
D1
Setting
D7
Error
(%)
0.00 51 (33h)
0.00 25 (19h)
0.00 12 (0Ch)
0.00 51 (33h)
0.00 34 (22h) 14285.71
0.00 25 (19h) 19230.77
0.00 16 (10h)
0.00 12 (0Ch) 38461.54
0.00
0.00
U2BRG
24. Serial Interface (UART2)
Setting
8 (08h)
Value
System Clock = 8 MHz
Stop bit
55555.56
29411.76
1201.92
2403.85
4807.69
9615.38
Actual
(bps)
Time
Setting
Error
(%)
-0.79
-3.55
0.16
0.16
0.16
0.16
0.16
2.12
0.16