R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 568

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 531 of 802
Table 24.12
Notes:
Source of UART2 bus
collision interrupt
Source of UART2
transmit/ NACK2 interrupt
(1, 6)
Source of UART2
receive/ACK2 interrupt
(1, 6)
Timing for transferring data
from UART receive shift
register to U2RB register
UART2 transmission output
delay
TXD2/SDA2 functions
RXD2/SCL2 functions
CLK2 function
Noise filter width
Read of RXD2 and SCL2
pin levels
Initial value of TXD2 and
SDA2 outputs
Initial and end values of
SCL2
DTC source number 14
DTC source number 15
Storage of receive data
Read of receive data
1.
2.
3.
4.
5.
6.
If the source of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1
(interrupt requested). (Refer to 11.8 Notes on Interrupts .)
If one of the bits listed below is changed, the interrupt source, the interrupt timing, and others change. Always be sure to set the IR bit to 0
(interrupt not requested) after changing these bits:
Bits SMD2 to SMD0 in the U2MR register, the IICM bit in the U2SMR register, the IICM2 bit in the U2SMR2 register, and the CKPH bit in the
U2SMR3 register.
Set the initial value of SDA2 output while bits SMD2 to SMD0 in the U2MR register are 000b (serial interface disabled).
Second data transfer to the U2RB register (rising edge of SCL2 9th bit)
First data transfer to the U2RB register (falling edge of SCL2 9th bit)
Refer to Figure 24.16 STSPSEL Bit Functions .
Refer to Figure 24.14 Transfer to U2RB Register and Interrupt Timing .
Function
(1, 5)
I
2
C Mode Functions
(6)
(6)
UART2 transmission
Transmission started or
completed (selectable by
U2IRS bit)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
No delay
TXD2 output
RXD2 input
CLK2 input or output port
selected
15 ns
Enabled when the
corresponding port
direction bit = 0
CKPOL = 0 (high)
CKPOL = 1 (low)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
UART2 transmission
Transmission started or
completed (selectable by
U2IRS bit)
The 1st to 8th bits of the
received data are stored
in bits b0 to b7 in the
U2RB register.
The U2RB register status is read.
(SMD2 to SMD0 = 001b,
Clock Synchronous
Serial I/O Mode
IICM = 0)
Oct 30, 2009
Start condition detection or stop condition detection
(Refer to Table 24.13 STSPSEL Bit Functions )
No acknowledgment
detection (NACK)
Rising edge of SCL2 9th bit
Acknowledgment detection (ACK)
Rising edge of SCL2 9th bit
Rising edge of SCL2 9th bit
With delay
SDA2 I/O
SCL2 I/O
200 ns
Enabled regardless of the content of the corresponding port direction bit.
The value set in the port register before setting I
High
Acknowledgment detection (ACK)
UART2 transmission
Rising edge of SCL2
9th bit
The 1st to 8th bits of the received data are
stored in bits b7 to b0 in the U2RB register.
(No Clock Delay)
(Usable in I
CKPH = 0
IICM2 = 0 (NACK/ACK interrupt)
2
C mode.)
Low
UART2 transmission
Falling edge of SCL2
next to 9th bit
I
2
(With Clock Delay)
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
CKPH = 1
UART2
transmission
Rising edge of
SCL2 9th bit
UART2 reception
Falling edge of SCL2 9th bit
Falling edge of
SCL2 9th bit
High
UART2 reception
Falling edge of SCL2 9th bit
UART2
transmission
Rising edge of
SCL2 9th bit
The 1st to 7th bits of the received data are
stored in bits b6 to b0 in the U2RB register.
8th bit is stored in bit b8 in the U2RB register.
IICM2 = 1 (UART transmit/receive interrupt)
(No Clock Delay)
2
C mode.
CKPH = 0
24. Serial Interface (UART2)
(2)
UART2 transmission
Falling edge of SCL2
next to 9th bit
Falling and rising edges
of SCL2 9th bit
Low
UART2 transmission
Falling edge of SCL2
next to 9th bit
The 1st to 8th bits are
stored in bits b7 to b0 in
the U2RB register.
Bits b6 to b0 in the
U2RB register are read
as bits b7 to b1. Bit b8
in the U2RB register is
read as bit b0.
(With Clock Delay)
CKPH = 1
(4)
(3)