R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 473

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 436 of 802
21.3
Figure 21.4
Table 21.4
fC4
f32
Count sources
Count operations
Count periods
Count start condition
Count stop condition
Interrupt request generation
timing
TREO pin function
Read from timer
Write to timer
Selectable functions
f4
f8
TRERST, TOENA: Bits in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2, RCS4 to RCS6: Bits in TRECSR register
In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and a
compare value match is detected with the 8-bit counter. Figure 21.4 shows a Block Diagram of Output Compare
Mode, Table 21.4 lists the Output Compare Mode Specifications, and Figure 21.5 shows an Operating Example
in Output Compare Mode.
= 01b
= 10b
Output Compare Mode
= 11b
RCS1 to RCS0
= 00b
Item
Output Compare Mode Specifications
Block Diagram of Output Compare Mode
1/2
Oct 30, 2009
f4, f8, f32, fC4
• Increment
• When the 8-bit counter value matches the TREMIN register content, the value is
• When RCS2 = 0 (4-bit counter is not used)
• When RCS2 = 1 (4-bit counter is used)
fi: Frequency of count source
n: Value set in TREMIN register
1 (count starts) is written to the TSTART bit in the TRECR1 register.
0 (count stops) is written to the TSTART bit in the TRECR1 register.
When the contents of the 8-bit counter and the TREMIN register match.
Select either one of the following:
• Programmable I/O port
• Output of f2, fC, f4, or f8
• Compare output
When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops),
writing to the TREMIN register is enabled.
• Selectable use of 4-bit counter
• Compare output function
set back to 00h and the count continues.
The count value is retained while the count stops.
1/fi x 2 x (n+1)
1/fi x 32 x (n+1)
Every time the 8-bit counter value matches the TREMIN register content, the
TREO output polarity is inverted. The TREO pin outputs a low-level signal after
reset is deasserted and timer RE is reset by the TRERST bit in the TRECR1
register. The output level is retained by setting the TSTART bit to 0 (count stops).
counter
4-bit
TRESEC
RCS2 = 1
RCS2 = 0
Data bus
Comparison
TREMIN
counter
circuit
8-bit
Match
signal
Specification
T Q
fC
f2
R
RCS6 to RCS4
=010b
=001b
=100b
=000b
=110b
COMIE
Reset
TRERST
TOENA
Timer RE interrupt
21. Timer RE
TREO pin