R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 646

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 609 of 802
Figure 27.17
Notes:
1. Do not generate interrupts while processing steps (1) to (3).
2. For 1 byte of data reception, skip steps (2) to (6) after step (1) and jump to process step (7).
Process step (8) is a dummy read from the ICDRR register.
ICSR register
ICCR1 register
ICSR register
ICIER register
ICIER register
ICCR1 register
ICSR register
ICCR2 register
ICCR1 register
ICCR1 register
Read the RDRF bit in the ICSR register
Read the RDRF bit in the ICSR register
Read the STOP bit in the ICSR register
Dummy read the ICDRR register
Register Setting Example in Master Receive Mode (I
No
No
No
Read the ICDRR register
Read the ICDRR register
Read the ICDRR register
Master receive mode
Last receive - 1?
Yes
Yes
Yes
RDRF = 1?
RDRF = 1?
STOP = 1?
ACKBT bit
ACKBT bit
TEND bit
TDRE bit
RCVD bit
STOP bit
RCVD bit
End
BBSY bit
TRS bit
SCP bit
MST bit
No
Oct 30, 2009
0
0
0
0
1
1
0
Yes
0
0
0
0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(1) Set the TEND bit to 0 and set to master receive mode.
(2) Set the ACKBT bit to the transmit device.
(3) Dummy read the ICDRR register.
(4) Wait until 1 byte is received.
(5) Determine (last receive - 1).
(6) Read the receive data.
(7) Set the ACKBT bit of the last byte and set continuous
(8) Read the receive data of (last byte - 1).
(9) Wait until the last byte is received.
(10) Set the STOP bit to 0.
(11) Generate a stop condition.
(12) Wait until a stop condition is generated.
(13) Read the receive data of the last byte.
(14) Set the RCVD bit to 0.
(15) Set to slave receive mode.
Set the TDRE bit to 0.
receive operation to disable (RCVD = 1).
2
C bus Interface Mode)
(1,2)
(1)
27. I
(2)
(1)
2
C bus Interface