R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 512

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 475 of 802
22.8
Figure 22.21
Table 22.13
Timer RG generates a timer RG interrupt request from four sources. The timer RG interrupt uses the single TRGIC
register (bits IR and ILVL0 to ILVL2) and a single vector.
Table 22.13 lists the Registers Associated with Timer RG Interrupt, and Figure 22.21 is a Block Diagram of Timer
RG Interrupt.
Like other maskable interrupts, the timer RG interrupt is controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because
a single interrupt source (timer RG interrupt) is generated from multiple interrupt request sources.
• The IR bit in the TRGIC register is set to 1 (interrupt requested) when a bit in the TRGSR register is set to 1
• The IR bit is set to 0 (no interrupt requested) when either the bit in the TRGSR register or the corresponding
• If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not
• If multiple bits in the TRGIER register are set to 1, use the TRGSR register to determine the source of the
• The bits in the TRGSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to
Refer to 22.2.4 Timer RG Interrupt Enable Register (TRGIER), for details of the TRGIER register.
Refer to 11.3 Interrupt Control, for details of the TRGIC register and 11.1.5.2 Relocatable Vector Tables,
for information on interrupt vectors.
Status Register
and the corresponding bit in the TRGIER register is also set to 1 (interrupt enabled).
bit in the TRGIER register is set to 0, or both are set to 0. In other words, the interrupt request is not
maintained even if the IR bit is once set to 1 but the interrupt is not acknowledged.
change.
interrupt request.
0 within the interrupt routine. Refer to 22.2.5 Timer RG Status Register (TRGSR), for the procedure for
setting these bits to 0.
Timer RG Interrupt
Timer RG
TRGSR
Registers Associated with Timer RG Interrupt
Block Diagram of Timer RG Interrupt
IMFA, IMFB, UDF, OVF: Bits in TRGSR register
IMIEA, IMIEB, UDIE, OVIE: Bits in TRGIER register
Oct 30, 2009
IMIEA bit
IMIEB bit
IMFA bit
IMFB bit
UDIE bit
OVIE bit
UDF bit
OVF bit
Interrupt Enable Register
Timer RG
TRGIER
Timer RG interrupt request
(IR bit in TRGIC register)
Interrupt Control Register
Timer RG
TRGIC
22. Timer RG