R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 808

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 771 of 802
35.12 Notes on Timer RG
Figure 35.7
35.13 Notes on Serial Interface (UARTi (i = 0 or 1))
35.12.1 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
35.12.2 Timer RG Counter (TRG)
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•
When reading data from the UiRB (i = 0 or 1) register either in clock synchronous serial I/O mode or in clock
asynchronous serial I/O mode, always read data in 16-bit units.
When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in
the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
When writing data to the UiTB register in clock asynchronous serial I/O mode with 9-bit transfer data length,
write data to the high-order byte first and then the low-order byte, in 8-bit units.
The phase difference and overlap between the external input signals from pins TRGCLKA and TRGCLKB
should be 1.5 f1 or more, respectively. The pulse width should be 2.5 f1 or more. Figure 35.7 shows the Phase
Difference, Overlap, and Pulse Width in Phase Counting Mode.
When writing to the TRG register or TRGCR register, make sure the TSTART bit in the TRGMR register to 0
(count stops).
Program example to read the receive buffer register:
Program example to write to the transmit buffer register:
TRGCLKA input
TRGCLKB input
MOV.W
MOV.B
MOV.B
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
00A6H,R0
#XXH,00A3H
#XXH,00A2H
Phase difference
Oct 30, 2009
Overlap
; Read the U0RB register
; Write to the high-order byte of the U0TB register
; Write to the low-order byte of the U0TB register
Phase difference
Overlap
Pulse width
Phase difference and overlap: 1.5 f1 or more
Pulse width: 2.5 f1 or more
Pulse width
35. Usage Notes