R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 712

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 675 of 802
Figure 32.4
32.4.1
32.4.2
32.4.3
32.4.4
CL2
CL1
VL4
VL3
VL2
VL1
All of the segment output pins SEG0 to SEG55 and common output pins COM0 to COM7 are shared with I/O
ports. Since all these pins function as I/O ports after a reset, set the corresponding LSEi bit (i = 00 to 59) to 1 for
the pins to be used as segment output and common output for LCD displays. Set the corresponding LSEi bit to
0 (I/O port) for the pins not to be used as segment output and common output. If these pins are not used as
I/O ports, perform unassigned pin handling for I/O ports (refer to Table 6.25 Unassigned Pin Handling).
Either f32 or fC-LCD is selected as the LCD clock source by setting bits LCKS0 and LCKS1. The division ratio
is selected from a range of divide-by-1 to divide-by-64 by setting bits LPSC0 to LPSC2.
The LCD data display control function is used to blink, or to invert an LCD display. This function is enabled by
setting the LDSPC bit to 1. A display is blinked by setting the LRVRS bit to 0 and inverted by setting the bit to
1. The interval for blinking or inverting is selected by bits LDFR0 to LDFR2.
The bias is controlled by connecting external division resistors to LCD power supply pins VL1 to VL4 or by
using the voltage multiplier. Figure 32.4 shows the Pin Connection and Voltage Levels when Division Resistors
are Connected Externally. Figure 32.5 shows the Pin Connection and Voltage Levels when Voltage Multiplier
is Used.
To connect division resistors externally, set the LVUPE bit to 0. Leave pins CL1 and CL2 open by setting the
LSE60 bit to 1. These pins can also be used as I/O ports by setting the LSE60 bit to 0.
To use the voltage multiplier, set the LVUPE bit to 1. Select the reference voltage VL1 for the voltage
multiplier to input externally or generate one internally by using the LVURS bit. Connect the voltage multiplier
capacitor between pins CL1 and CL2. To generate the voltage internally, select the VL1 voltage value by
setting bits LVLS0 to LVLS3. The wait time for the voltage multiplier is selected from the count source
count source 64 using bits LVW0 and LVW1.
Contrast adjustment
1/4 bias selected
Open
Open
VLDC
3/4 VLDC
2/4 VLDC
1/4 VLDC
Segment Output Pin Selection
LCD Clock Selection
LCD Data Display Control
Bias Control
Externally
Pin Connection and Voltage Levels when Division Resistors are Connected
R4
R3
R2
R1
C4
C3
C2
C1
Oct 30, 2009
Note:
1. Pins CL1 and CL2 can be used as I/O ports.
CL2
CL1
VL4
VL3
VL2
VL1
Contrast adjustment
1/3 bias selected
Open
Open
VLDC
2/3 VLDC
1/3 VLDC
R4
R2
R1
C4
C2
C1
CL2
CL1
VL4
VL3
VL2
VL1
32. LCD Drive Control Circuit
Contrast adjustment
1/2 bias selected
VLDC
Open
Open
1/2 VLDC
R4
R1
C4
C1
8 to