R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 543

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 506 of 802
24.2.7
Note:
24.2.8
Note:
1. The RXD2 digital filter can be used only in clock asynchronous serial I/O (UART) mode. When bits SMD2 to
1. When the MP bit is set to 1 (multiprocessor communication enabled), the settings of bits PRY and PRYE in the
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00B0h
Address 00BBh
SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or 010b (I
DF2EN bit to 0 (RXD2 digital filter disabled).
U2MR register are disabled. If bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous
serial I/O mode), set the MP bit to 0 (multiprocessor communication disabled).
Symbol
Symbol
Symbol
Symbol
DF2EN RXD2 digital filter enable bit
Bit
Bit
MPIE
UART2 Digital Filter Function Select Register (URXDF)
UART2 Special Mode Register 5 (U2SMR5)
MP
—
—
—
—
—
—
—
—
—
—
—
—
—
b7
b7
—
—
0
0
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Multiprocessor communication
enable bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Multiprocessor communication
control bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bit
b6
b6
—
—
0
0
Oct 30, 2009
Bit Name
Bit Name
b5
—
b5
—
0
0
(1)
MPIE
b4
b4
—
0
0
0: RXD2 digital filter disabled
1: RXD2 digital filter enabled
0: Multiprocessor communication disabled
1: Multiprocessor communication enabled
When the MP bit is set to 1 (multiprocessor
communication enabled), this bit is enabled.
When the MPIE bit is set to 1, the following will
result:
• Receive data in which the multiprocessor bit is 0
• On receiving receive data in which the
Set to 0.
is ignored. The settings of the RI bit in the U2C1
register and bits OER and FER in the U2RB
register to 1 are disabled.
multiprocessor bit is 1, the MPIE bit is set to 0 and
receive operation other than multiprocessor
communication is performed.
b3
b3
—
—
0
0
DF2EN
b2
b2
—
0
0
Function
Function
b1
b1
—
—
0
0
24. Serial Interface (UART2)
MP
b0
b0
—
0
0
2
C mode), set the
(1)
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—