R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 603

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 566 of 802
Figure 26.7
26.4.3
RDRF bit in
SSSR register
RSSTP bit in
SSCRH register
Figure 26.7 shows an Example of Synchronous Serial Communication Unit Operation during Data Reception
(Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer Length). During data reception, the
synchronous serial communication unit operates as described below (the data transfer length can be set from 8
to 16 bits using the SSBR register).
When the synchronous serial communication unit is set as the master device, it outputs a synchronous clock and
inputs data. When the synchronous serial communication unit is set as a slave device, it inputs data
synchronized with the input clock.
When the synchronous serial communication unit is set as the master device, it outputs a receive clock and
starts receiving by performing dummy read from the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled) at this time, an RXI interrupt request is generated. If the SSDR register is read, the
RDRF bit is automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (receive operation is completed
after receiving 1 byte of data). The synchronous serial communication unit outputs a clock for receiving 8 bits
of data and stops. After that, set the RE bit in the SSER register to 0 (reception disabled) and the RSSTP bit to 0
(receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (reception enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.
Confirm that the ORER bit is set to 0 before restarting reception.
Figure 26.8 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
Program
processing
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at even edges),
Data Reception
CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits)
SSCK
Example of Synchronous Serial Communication Unit Operation during Data
Reception (Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer
Length)
SSI
1
0
1
0
Dummy read
the SSRDR register.
Oct 30, 2009
b0
RXI interrupt request
generation
1 frame
Read data from
the SSRDR register.
b7
b0
RXI interrupt request
generation
26. Synchronous Serial Communication Unit (SSU)
1 frame
Set the RSSTP bit to 1.
BS0 to BS3: Bits in SSBR register
CPHS, CPOS: Bits in SSMR register
SSUMS: Bit in SSMR2 register
b7
b0
Read data from
the SSRDR register.
RXI interrupt request
generation
b7