R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 337

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 300 of 802
19.7.1
Notes:
Table 19.14
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Note:
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRD
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for waveform output (refer to 6.6 Port Settings ), the initial output level is output when the
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Register
1. Do not set registers TRCGRB and TRCGRC to the same value.
Address 0121h
TRCCR1 register is set.
Symbol
Symbol
Bit
CCLR
TCK0
TCK1
TCK2
TOA
TOB
TOC
TOD
Timer RC Control Register 1 (TRCCR1) in PWM2 Mode
BFC = 0
BFD = 0
BFD = 1
CCLR
Functions of TRCGRj Register in PWM2 Mode
b7
0
Setting
TRCIOA output level select bit
TRCIOB output level select bit
TRCIOC output level select bit
TRCIOD output level select bit
Count source select bit
TRC counter clear select bit
TCK2
b6
0
General register. Set the PWM period.
General register. Set the PWM output change point.
General register. Set the PWM output change point (wait time
after trigger).
Buffer register. Set the next PWM output change point. (Refer to
19.3.2 Buffer Operation .)
Oct 30, 2009
(Not used in PWM2 mode.)
Bit Name
TCK1
b5
0
(1)
TCK0
b4
(1)
(1, 2)
(1)
(1)
0
Register Function
0: Clear disabled (free-running operation)
Disabled in PWM2 mode.
0: Active level is high
1: Active level is low
Disabled in PWM2 mode.
b6 b5 b4
1: Clear by compare match with the TRCGRA register
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: Do not set.
1 1 1: Do not set.
(Initial output at low
High-level output at compare match with
the TRCGRC register
Low-level output at compare match with
the TRCGRB register)
(Initial output at high
Low-level output at compare match with
the TRCGRC register
High-level output at compare match with
the TRCGRB register)
TOD
b3
0
TOC
b2
0
Function
TOB
b1
0
TOA
b0
0
TRCIOB pin
TRCIOB pin
PWM2 Output Pin
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W