R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 440

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 403 of 802
Table 20.15
i = 0 or 1, j = either A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0, TRDIOB0 pins
function
TRDIOC0, TRDIOD0, TRDIOA1
to TRDIOD1 pins function
INT0 pin function
Read from timer
Write to timer
Selectable functions
PWM3 Mode Specifications
Item
Oct 30, 2009
f1, f2, f4, f8, or f32
The TRD0 register is incremented (TRD1 register is not used).
PWM period: 1/fk × (m+1)
Active level width of TRDIOA0 output: 1/fk × (m-n)
Active level width of TRDIOB0 output: 1/fk × (p-q)
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• Compare match (The contents of the TRDi register and the
• TRD0 register overflow
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse
• Buffer operation (Refer to 20.2.2 Buffer Operation. )
• Active level selectable for each individual pin
• A/D trigger generation
fk: Frequency of count source
m: Value set in TRDGRA0 register
n: Value set in TRDGRA1 register
p: Value set in TRDGRB0 register
q: Value set in TRDGRB1 register
register when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
stops at compare match with the TRDGRA0 register.
The PWM output pin holds the level after the output changes by the
compare match.
TRDGRji register match.)
Output Forced Cutoff. )
TRDIOA0 output
TRDIOB0 output
m+1
n+1
p+1
q+1
p-q
Specification
(Active level is high)
m-n
20. Timer RD