R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 528

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 491 of 802
23.4
Table 23.5
i = 0 or 1
Note:
Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
The UART mode allows data transmission and reception after setting the desired transfer rate and transfer data
format.
Table 23.5 lists the UART Mode Specifications, and Table 23.6 lists the Registers Used and Settings in UART
Mode.
1. If an overrun error occurs, the receive data (b0 to b8) in the UiRB register will be undefined.
The IR bit in the SiRIC register remains unchanged.
Clock Asynchronous Serial I/O (UART) Mode
Item
UART Mode Specifications
Oct 30, 2009
• Character bits (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bits: Selectable from 1 or 2 bits
• The CKDIR bit in the UiMR register is set to 0 (internal clock): fj/(16(n+1))
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
• To start transmission, the following requirements must be met:
• To start reception, the following requirements must be met:
• For transmission, one of the following can be selected.
• For reception
• Overrun error
• Framing error
• Parity error
• Error sum flag
fj = f1, f8, f32, fC n = Value set in UiBRG register: 00h to FFh
fEXT: Input from CLKi pin,
n = Value set in UiBRG register: 00h to FFh
- The TE bit in the UiC1 register is set to 1 (transmission enabled).
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register).
- The RE bit in the UiC1 register is set to 1 (reception enabled).
- Start bit detection
- The UiIRS bit is set to 0 (transmit buffer empty):
- The UiIRS bit is set to 1 (transfer completed):
When data is transferred from the UARTi receive register to the UiRB
register (at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data
before reading the UiRB register and receive the bit one before the last
stop bit of the next unit of data.
This error occurs when the set number of stop bits is not detected.
This error occurs when parity is enabled, and the number of 1’s in the
parity and character bits do not match the set number of 1’s.
This flag is set to 1 if an overrun, framing, or parity error occurs.
When data is transferred from the UiTB register to the UARTi transmit
register (at start of transmission).
When data transmission from the UARTi transmit register is completed.
(1)
Specification
23. Serial Interface (UARTi (i = 0 or 1))