R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 508

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 471 of 802
22.7
Table 22.11
j = A or B
Table 22.12
Count source
Count operations
Count start condition
Count stop condition
Interrupt request generation
timing
TRGIOA pin function
TRGIOB pin function
TRGCLKA/TRGCLKB
pins function
Read from timer
Write to timer
Selectable functions
TRGCLKB pin
TRGCLKA pin
to CNTEN0 in
Bits CNTEN7
In phase counting mode, the phase difference between the external input signals from two pins TRGCLKA and
TRGCLKB is detected and the TRG register is incremented or decremented.
When phase counting mode is selected while the bits TRGCLKASEL0 and TRGCLKBSEL0 are set to 1,
regardless of the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 in the TRGCR register, pins
TRGCLKA and TRGCLKB automatically function as external clock input pins and the TRG register is
incrermented or decremented by setting bits CNTEN0 to CNTEN7 in the TRGCNTC register. However, bits
CCLR0 and CCLR1 in the TRGCR register and registers TRGIOR, TRGIER, TRGSR, TRGGRA, and TRGGRB
are enabled, so the input capture/output compare function, PWM output function, and interrupt sources can be
used.
The TRG register operates counting at both the rising and falling edges of the TRGCLKA or TRGCLKB pin by
setting bits CNTEN0 to CNTEN7. Table 22.11 lists the Phase Counting Mode Specifications, and Table 22.12 lists
the Increment and Decrement Conditions for TRG Register.
TRGCNTC
direction
register
Count
Value
Phase Counting Mode
Item
Phase Counting Mode Specifications
Increment and Decrement Conditions for TRG Register
CNTEN7
0
Low
1
1
CNTEN6
0
Oct 30, 2009
High
External signal input to the TRGCLKj pin
1 (count starts) is written to the TSTART bit in the TRGMR register.
The count value can be read by reading the TRG register.
The TRG register can be written to.
Increment/decrement
0 (count stops) is written to the TSTART bit in the TRGMR register.
• Input capture (active edge of the TRGIOj input)
• Compare match (the contents of the TRG register and the TRGGRj
• TRG register underflow
• TRG register overflow
Programmable I/O port, input-capture input, output-compare output, or
PWM output
Programmable I/O port, input-capture input, or output-compare output
External clock input
• Selection of counter increment and decrement conditions
• The input capture/output compare function and PWM function can be
1
register match)
Selectable by bits CNTEN7 to CNTEN0 bits in the TRGCNTC register.
used.
1
CNTEN5
0
High
1
1
CNTEN4
0
Low
1
1
CNTEN3
0
Specification
High
1
1
CNTEN2
0
Low
1
1
CNTEN1
0
Low
1
1
22. Timer RG
CNTEN0
0
High
1
1