R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 504

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 467 of 802
22.6
Table 22.8
j = A or B
Table 22.9
Count sources
Count operation
PWM waveform
Count start condition
Count stop condition
Interrupt request generation
timing
TRGIOA pin function
TRGIOB pin function
TRGCLKA/TRGCLKB
pins function
Read from timer
Write to timer
Selectable functions
In PWM mode, registers TRGGRA and TRGGRB are used as a pair and a PWM waveform is output from the
TRGIOA output pin. The output setting in the TRGIOR register is invalid for the pins set to PWM mode. Set the
high-level output timing for PWM waveforms in the TRGGRA register and the low-level output timing for PWM
waveforms in the TRGGRB register.
By selecting a compare match with either the TRGGRA or TRGGRB register as the counter clear source for the
TRG register, a PWM waveform with a duty of 0% to 100% can be output from the TRGIOA pin.
Table 22.8 lists the PWM Mode Specifications, and Table 22.9 lists the Combination of PWM Output Pins and
Registers. When the setting values of registers TRGGRA and TRGGRB are the same, the output value does not
change even if a compare match occurs.
Output Pin
TRGIOA
TRGIOB
PWM Mode
Item
PWM Mode Specifications
Combination of PWM Output Pins and Registers
High-Level Output
TRGGRA
I/O port function
Oct 30, 2009
f1, f4, f8, f32, or
1 (count starts) is written to the TSTART bit in the TRGMR register.
The count value can be read by reading the TRG register.
The TRG register can be written to.
external signal input to the TRGCLKj pin (active edge selectable by a
program)
Increment
• The high-level output timing for PWM waveforms is set in
• The low-level output timing for PWM waveforms is set in
0 (count stops) is written to the TSTART bit in the TRGMR register.
• Compare match (the contents of the TRG register and the TRGRj
• TRG register overflow
PWM output
Programmable I/O port
Programmable I/O port or external clock input
• Timing for setting the TRG register to 0000h
• Buffer operation (Refer to 22.3.2 Buffer Operation .)
the TRGGRA register.
the TRGGRB register.
register match)
Overflow or compare match with the TRGGRj register
Low-Level Output
TRGGRB
Specification
22. Timer RG